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«UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-K (Mark One) È ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE ...»

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UNITED STATES

SECURITIES AND EXCHANGE COMMISSION

Washington, D.C. 20549

FORM 10-K

(Mark One)

È ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE

ACT OF 1934

For the fiscal year ended January 2, 2016

OR

‘ TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE

ACT OF 1934 For the transition period from to.

Commission file number 0-15867

CADENCE DESIGN SYSTEMS, INC.

(Exact name of registrant as specified in its charter) Delaware 00-0000000 (State or Other Jurisdiction of (I.R.S. Employer Incorporation or Organization) Identification No.) 2655 Seely Avenue, Building 5, San Jose, California 95134 (Address of Principal Executive Offices) (Zip Code) (408) 943-1234 (Registrant’s Telephone Number, including Area Code)

Securities registered pursuant to Section 12(b) of the Act:

Title of Each Class Names of Each Exchange on which Registered Common Stock, $0.01 par value per share NASDAQ Global Select Market

Securities registered pursuant to Section 12(g) of the Act:

None Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes [ X ] No [ ] Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes [ ] No [ X ] Indicate by check mark whether the registrant: (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes [ X ] No [ ] Indicate by check mark whether the registrant has submitted electronically and posted on its corporate Web site, if any, every Interactive Data File required to be submitted and posted pursuant to Rule 405 of Regulation S-T (§ 232.405 of this chapter) during the preceding 12 months (or for such shorter period that the registrant was required to submit and post such files). Yes [ X ] No [ ] Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. [ ] Indicate by check mark whether the registrant is a large accelerated filer, an accelerated filer, a non-accelerated filer, or a smaller reporting company. See the definitions of “large accelerated filer,” “accelerated filer,” and “smaller reporting

company” in Rule 12b-2 of the Exchange Act. (check one):

Large accelerated filer [ X ] Accelerated filer [ ] Non-accelerated filer [ ] Smaller reporting company [ ] (Do not check if a smaller reporting company) Indicate by check mark whether the registrant is a shell company (as defined in Rule 12b-2 of the Act). Yes [ ] No [ X ] The aggregate market value of the voting and non-voting common equity held by non-affiliates computed by reference to the price at which the common equity was last sold as of the last business day of the registrant’s most recently completed second fiscal quarter ended July 4, 2015 was approximately $5,641,117,000.

On February 6, 2016, approximately 305,358,000 shares of the Registrant’s Common Stock, $0.01 par value, were outstanding.

DOCUMENTS INCORPORATED BY REFERENCE

Portions of the definitive proxy statement for Cadence Design Systems, Inc.’s 2016 Annual Meeting of Stockholders are incorporated by reference into Part III hereof.

CADENCE DESIGN SYSTEMS, INC.

ANNUAL REPORT ON FORM 10-K FOR THE FISCAL YEAR ENDED JANUARY 2, 2016 Table of Contents

–  –  –

Item 1. Business This Annual Report on Form 10-K and the documents incorporated by reference in this Annual Report on Form 10-K contain statements that are not historical in nature, are predictive, or that depend upon or refer to future events or conditions or contain other forward-looking statements.

Statements including, but not limited to, statements regarding the extent and timing of future revenues and expenses and customer demand, statements regarding the deployment of our products, statements regarding our reliance on third parties and other statements using words such as “anticipates,” “believes,” “could,” “estimates,” “expects,” “forecasts,” “intends,” “may,” “plans,” “projects,” “should,” “will” and “would,” and words of similar import and the negatives thereof, constitute forward-looking statements. These statements are predictions based upon our current expectations about future events. Actual results could vary materially as a result of certain factors, including but not limited to those expressed in these statements. Important risks and uncertainties that could cause actual results to differ materially from those contained in the forward-looking statements include, but are not limited to, those identified in the “Proprietary Technology,” “Competition,” “Risk Factors,” “Critical Accounting Estimates,” “Results of Operations,” “Quantitative and Qualitative Disclosures About Market Risk” and “Liquidity and Capital Resources” sections contained in this Annual Report on Form 10-K and the risks discussed in our other Securities Exchange Commission, or SEC, filings.





We urge you to consider these factors carefully in evaluating the forward-looking statements contained in this Annual Report on Form 10-K. All subsequent written or oral forward-looking statements attributable to our company or persons acting on our behalf are expressly qualified in their entirety by these cautionary statements.

The forward-looking statements included in this Annual Report on Form 10-K are made only as of the date of this Annual Report on Form 10-K. We do not intend, and undertake no obligation, to update these forwardlooking statements.

Fiscal Year End Our fiscal year ends on the Saturday closest to December 31. Fiscal 2015 and fiscal 2013 were 52-week years, whereas fiscal 2014 was a 53-week year. Revenue and expenses included in the results of operations for fiscal 2014 were impacted by the additional week.

Overview We develop system design enablement, or SDE, solutions that our customers use to design whole electronics systems, increasingly small and complex integrated circuits, or ICs, and electronic devices. Our solutions are designed to help our customers reduce the time to bring an electronics system, IC or electronic device to market and to reduce their design, development and manufacturing costs. Our SDE product offerings include electronic design automation, or EDA, software, emulation and prototyping hardware, system interconnect and analysis and two categories of intellectual property, or IP, commonly referred to as verification IP, or VIP, and design IP. We provide maintenance for our software, hardware, and IP product offerings. We also provide engineering services related to methodology, education, hosted design solutions and design services for advanced ICs and development of custom IP. These services help our customers manage and accelerate their electronics product development processes.

Our customers include electronics systems and semiconductor companies, internet infrastructure and service companies and other technology companies that develop a wide range of electronics products and services in a number of market segments, such as mobile and consumer devices, communications, cloud and data center infrastructure, personal computers, automotive systems, medical systems, and other devices. The renewal of many of our customer contracts and our customers’ decisions to make new purchases from us are dependent upon our customers’ commencement of new design projects. As a result, our business is significantly influenced by our customers’ business outlook and investment in new designs and products.

Corporate Information We were organized as a Delaware corporation in June 1988. Our headquarters is located at 2655 Seely Avenue, San Jose, California 95134. Our telephone number is (408) 943-1234. We use our website at www.cadence.com to communicate important information about our company, including news releases and financial information. Our website permits investors to subscribe to e-mail notification alerts when we post new material information on our website. We also make available on our investor relations webpage, free of charge, copies of our SEC filings and submissions as soon as reasonably practicable after electronically filing or furnishing such documents with the SEC. Stockholders may also request copies of these documents by writing to our Corporate Secretary at the address above. Information on our website is not incorporated by reference in this Annual Report on Form 10-K unless expressly noted.

The EDA and IP Industries as Drivers for Our Business Our system design enablement strategy is to deliver the technologies necessary for integrated system and system-on-chip, or SOC, design with an end product in mind. At the heart of this strategy is our growing core EDA business, which is complemented by our expanding businesses in IP, system interconnect and analysis, system level design and hardware-software development.

Our customers commence new design projects based on end-user demand for electronics systems, ICs and devices that are smaller, use less power and provide more functionality. To meet this demand, our customers design and develop new ICs and electronic devices and systems using our products and services.

The markets our customers serve are sensitive to end product price, performance and the time it takes to bring their products to market. In order to be competitive and profitable in these markets, our customers demand high levels of productivity from their design teams, better predictability in shorter development schedules, high performance products and lower development and manufacturing costs. Semiconductor and electronics systems companies are responding to these challenges and users’ demand for increased functionality and smaller devices by combining subsystems (such as radio frequency, or RF, wireless communication, signal processing, microprocessors and memory controllers) onto a single silicon chip, creating a SoC or combining multiple chips into a single chip package in a format referred to as system-in-package, or SiP. The trend toward subsystem integration has required these chip makers to find solutions to challenges previously addressed by system companies, such as verifying system-level functionality and hardware-software interoperability, and has driven the need for incorporation of preverified commercial IP into these systems. In addition, whole systems must be designed and verified, made up of many component SoCs and software, and must be analyzed for performance in end-user operating scenarios.

Significant issues that our customers face in creating their products include designing and verifying whole systems including software, reducing power consumption, manufacturing microscopic circuitry, verifying device functionality and achieving technical performance targets, all while meeting aggressive time-to-market and cost requirements. We must deliver products that address these technical challenges while improving the productivity, predictability, reliability and profitability of the design processes and products of their customers.

Products and Product Strategy Our strategy is to provide our customers with the ability to address the broad range of issues that arise in systems, software, interconnect and silicon. Our products are engineered to improve our customers’ design productivity and design quality by providing a comprehensive set of SDE solutions, including EDA software, emulation and prototyping hardware and a differentiated portfolio of design IP and VIP. Product and maintenance revenue includes fees from licenses to use our software and IP, from sales and leases of our hardware products and from royalties generated by our customers’ shipment of their products containing certain types of our IP.

We combine our products and technologies into categories related to major design activities:

• Functional Verification, including Emulation and Prototyping Hardware;

• Digital IC Design and Signoff;

• Custom IC Design;

• System Interconnect and Analysis; and

• IP.

The products and technologies included in these categories are combined with ready-to-use packages of technologies assembled from our broad portfolio of IP and other associated components that provide comprehensive solutions for low power, mixed signal and designs at smaller geometries referred to as advanced process nodes, as well as popular designs based on design IP owned and licensed by other companies. These solutions are marketed to users who specialize in areas such as system design and verification, functional verification, logic design, digital implementation, custom IC design and verification, printed circuit board, or PCB, IC package and SiP design and analysis.

Functional Verification, including Emulation and Prototyping Hardware Functional verification products are used by our customers to efficiently and effectively verify that the circuitry they have designed will perform as intended. Verification takes place before implementing or manufacturing the circuitry, significantly reducing the risk of discovering an error in the completed product. Our functional verification offerings are comprised of two major categories: logic verification and system design and verification.

Our logic verification software offering consists of planning, testbench automation, simulation, hardware acceleration, JasperGold® formal verification and environment capabilities within the Incisive® functional verification platform and Palladium® verification computing platform. This offering enables our customers to coordinate verification activities across multiple teams and various specialists for verification planning and closure.



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